A variety of components are included in integrated circuits that affect the rate at which power is consumed. For example, delay lock loops are often found in memory devices and memory controllers to perform such functions as synchronizing one signal, such as a data strobe signal DQS, to another signal, such as an external clock signal. Conventional delay lock loops traditionally generate a clock signal that can be used to generate a signal, such as a DQS signal, that store data in a latch on each rising edge of the DQS signal. However, more recent memory devices are designed to latch data on both the rising edge of the DQS signal and the falling edge of the DQS signal. While an inverted version of the ClkOut signal could be used to latch data on the falling edge of the ClkOut signal, any deviation of the ClkOut signal from a 50% duty cycle would adversely affect the ability of the DQS signal to latch valid data, particularly with high-speed data transfers insofar as the transitions of the DQS signal should ideally occur at the center of the period that a data bit to be latched is valid.
One approach to providing signals that can be used to latch data on both transitions of a clock signal uses a delay locked loop (“DLL”) 10 as shown in FIG. 1. The DLL 10 includes a first variable delay line 14 that receives an input clock signal ClkIn and generates an output clock signal Clk 180 Out as a delayed version of the ClkIn signal. The amount of the delay is determined by a first delay control signal, DelCtrl-1. Similarly, a second variable delay line 16 receives the Clk 180 Out signal and generates an output signal with a delay determined by a second delay control signal, DelCtrl-2. The second variable delay line 16 can be identical to the first variable delay line 14 so that both of the delay lines 14, 16 provide the same delay to the ClkIn signal for the same values of the DelCtrl-1 and DelCtrl-2 signals. The DLL 10 also includes a phase detector 20 and a delay controller 24 coupled to the output of the phase detector 20 for adjusting the delay of the delay lines 14, 16. The phase detector 20 compares the phase of the input clock signal ClkIn to the phase of the signal output from the delay line 16 to generate a phase error signal. The phase error signal is applied to the delay controller 24. The delay controller 24 responds to the phase error signal by adjusting the value of the DelCtrl-1 and DelCtrl-2 signals in a manner that causes the delay lines 14, 16 to reduce the phase error. When the DLL 10 is locked, the signal output from the delay line 16 will have the same phase as the ClkIn signal. In an embodiment where the delay lines 14, 16 are identical to each other and the DelCtrl-1 and DelCtrl-2 signals are identical, the delay line 14 can output a CLK 180 Out signal having a phase that is 180 degrees from the phase of the ClkIn signal. The ClkIn signal, or the signal output from the delay line 16, can then be provided as a Clk 0 Out signal.
In operation, for the DLL 10 to be locked, it would be necessary for the delay lines 14, 16 to collectively delay the Clk 0 signal by 360 degrees. If both delay lines 14, 16 provide the same delay, the rising edge of the Clk 180 Out signal would then be delayed 180 degrees from the rising edge of the Clk 0 signal. As a result, the Clk 0 and Clk 180 Out signals could be used to latch data at the center of respective data valid periods.
Although the DLL 10 may provide improved performance for latching data on both transitions of the ClkIn signal, it nevertheless can suffer from a number of performance limitations. First, since the phase detector 20 determines a phase error only once each period of the ClkIn signal, it can require an undesirably long time for the DLL 10 to achieve a locked condition. Second, the rising edge of the Clk 180 Out signal is not locked to the falling edge of the ClkIn signal. As a result, any difference in the delay of the delay line 14 compared to the delay of the delay line 16 will result in a deviation of the rising edge of the Clk 180 Out signal from 180 degrees.
There is therefore a need for a duty cycle correction system and method that provides faster and more accurate control over the duty cycle of a clock signal.